This invention relates to error detection for digital transmission systems and in particular to error detection in submerged repeater supervisory systems.
In our British Patent Specification No. 1536337 (the contents of which are incorporated herein by reference) (corresponding to U.S. Pat. No. 4,121,195) is described a simple parity violation detector for detecting line errors in particular at a repeater.
According to claim 1 of Specification No. 1536337 there is provided an error detecting arrangement for a digital transmission line system over which constant accumulated disparity signals are transmitted, including at a transmitter means for modifying the signals for transmission at intervals whereby the transmitted signals contain special signals the digital values of which reflect the parity of predetermined digital signal events in the immediately preceding intervals, the special signals themselves having values which maintain the overall constant accumulated disparity of the transmitted signals, means at a subsequent point in the system for counting the predetermined digital signal events in the transmitted signals and means for determining a change in the dc content of the counting means output.
The same detector may also be used to receive information transmitted by intentionally violating parity i.e. for supervisory purposes. In a particular case of the known detector an extra bit is added to a scrambled data stream by digital multiplexing so that following n consecutive scrambled data bits there is one parity bit. Typically this comprises a 24B1P (nB1P or n binary data bits and one parity bit) line code, that is for every 24 binary data bits transmitted to line a 25th bit is added such that the 25 bit word has even mark parity. The parity bit is used to control the parity of each (n+1) bit block. In the known detector illustrated in FIG. 1, non return to zero (NRZ) data 1 and clock 2 are summed together at 3 to produce return to zero (RZ) pulses, a divide by two counter 4 (toggle) is caused to toggle on each received mark (or alternatively each received space). If the (n+1) bit blocks are coded to have even mark parity, then in the event of no errors, the output of the counter 4 will be in the same state immediately after each parity bit. In the event of a violation of even parity within a block, either by an odd number of errors occurring or by intentionally using the parity bit to make the block have odd parity, then the output of the counter 4 immediately after the parity bit will be in the opposite state to that immediately after the previous parity bit and the counter output will continue to take up this new state after each subsequent even mark parity block.
The output of the binary counter 4 has three components. Firstly a random component due to the scrambled data which at low frequencies [&lt;fo/4, where fo is the line digit frequency (bit rate)] has a substantially flat power spectral density, secondly a dc component due to the parity bit and thirdly a line spectrum also due to the parity bit. The information in the parity bit, be it line errors or a low speed data channel, can be separated from the background noise such as by low and band pass filters 7 and 5 respectively. Line errors are detected by a change in dc level detector 7a.
A practical difficulty with such an arrangement is that the bias produced is small and necessitates dc amplifiers with small offsets and low drift rates with temperature and aging. Another drawback is that at high error rates the bias changes become too rapid to pass through the low pass filter, resulting in no bias. The noise level that is present (energy in the bandwidth of the filter) is small and a very small offset will stop the threshold level of the counter being crossed and hence no errors will be detected in that case. Thus at high BERs (Bit Error Rates) the error detector cannot reliably tell if there are any errors at all.
One method of creating a low speed data channel is to intentionally violate even parity at a fixed frequency. A low speed signalling channel is thus created by switching the frequency on and off and detecting this at a repeater by a suitable filter tuned to the frequency, and for example demodulator (envelope detector) 6. In other words, periodic parity bit violations at a low rate produce a tone which can be used as a carrier for supervisory commands.
A modification to improve the high BER indication is to superimpose a triangular waveform on to the level detector input such that at high error rates the triangular waveform provides the threshold crossings, while at low or zero BERs the bias offset holds the triangular waveform away from the threshold. A particular triangular waveform we have employed is 1/4 of the bias change. However this modification cannot be guaranteed to function under all BER conditions as on some regenerators, unexplained offsets have been generated at very high BERs, such as with broken fibre and no light, causing the triangular waveform not to cross the threshold and hence no error indication.